Publication

SCI Journal Papers

J. Kim, Y. Jo, H. Park, T. Seong, Y. Lim*, and J. Choi*, " A 12.8–15.0-GHz Low-Jitter Fractional- N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2024. (* Co-Corresponding Authors). [Q1 / IF 5.4, Top Journal in Circuit Field]

Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2023. [Q1 / IF 5.4, Top Journal in Circuit Field]

Y. Lim, J. Kim, Y. Jo, J. Bang, and J. Choi*, "A Wide-Lock-In-Range and Low-Jitter 12-14.5-GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2022. [Q1 / IF 5.4, Top Journal in Circuit Field] 

S. Yoo, S. Choi, Y. Lee, T, Seong, Y. Lim, and J. Choi*, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator," IEEE Journal of Solid-State Circuits (JSSC), May. 2020. [Q1 / IF 5.4, Top Journal in Circuit Field] 

J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2019. [Q1 / IF 5.4, Top Journal in Circuit Field]

J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), Dec. 2019.

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2018. [Q1 / IF 5.4, Top Journal in Circuit Field] 

Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi*, "An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2018. [Q1 / IF 5.4, Top Journal in Circuit Field] 

K. Lim*, S. Lee, Y. Lee, ... Y. Lim, C. Song, J. Seong, J. Choi, and S. Han, "A 65nm CMOS 2×2 MIMO Multi-band LTE RF Transceiver for Small Cell Base Stations," IEEE Journal of Solid-State Circuits (JSSC), Jul. 2018. [Q1 / IF 5.4, Top Journal in Circuit Field] 

Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, and J. Choi*, "An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov. 2017. 

S. Choi, S. Yoo, Y. Lim, and J. Choi*, "A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," IEEE Journal of Solid-State Circuits (JSSC), Aug. 2016. [Q1 / IF 5.4, Top Journal in Circuit Field] 

H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi*, "A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers", IEEE Journal of Solid-State Circuits (JSSC), Mar. 2016. [Q1 / IF 5.4, Top Journal in Circuit Field] 

K. J. Han, Y. Lim, and Y. Kim*, "A Performance Analysis for Interconnections of 3D ICs with Frequency-Dependent TSV Model in S-parameter", Journal of Semiconductor Technology and Science, Oct. 2014.

International Conference Proceedings

J. Kim+, Y. Jo+, Y. Lim+, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi*, "A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (+ Co-First Authors). [Top Conference in Circuit Field, 반도체 올림픽] 

Y. Lim, J. Kim, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMjitter, 12-14.5GHz Subsampling PLL with a 150uW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. [Top Conference in Circuit Field, 반도체 올림픽] 

J. Kim+, H. Yoon+, Y. Lim+, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL," IEEE International Solid-State Circuits (ISSCC), Feb. 2019. (+ Co-First Authors). [Top Conference in Circuit Field, 반도체 올림픽] 

J. Lee, J. Bang, Y. Lim, and J. Choi*, "A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer," IEEE Symp. VLSI Circuits Dig., Jun. 2019.

S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A 140fsRMS-Jitter and −72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier," IEEE International Solid-State Circuits (ISSCC), Feb. 2019. [Top Conference in Circuit Field, 반도체 올림픽] 

Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi*, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "153 fs RMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. VLSI Circuits Dig., Jun. 2018.

H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim and J. Choi*, "Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G," IEEE International Solid-State Circuits (ISSCC), Feb. 2018. [Top Conference in Circuit Field, 반도체 올림픽] 

Y. Lim, J. Lee, S. Park, and J. Choi*, "An External-Capacitor-Less High-PSR Low-Dropout Regulator Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2018.

Y. Lim, J. Lee, S. Park, and J. Choi*, "An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," IEEE Custom Integrated Circuits Conference (CICC), May. 2017.